Designing and testing a computer architecture is an extremely complex process, involving a range of tasks from the high level such as specifying the architecture down to the low level such as determining the physical placement of transistors on a silicon substrate. Each stage of the design process requires extensive testing and verification of the design through that stage. The computer architecture is typically simulated during the design process before building and testing the hardware.
The testing process is complicated further for architectures supporting multiple cache memories. For example, a computer architecture may support multiple processors having either a shared memory, multiple dedicated memories, or both, as well as multiple cache memories (referred to hereinafter simply as caches). Multiple memory agents are also provided to handle memory operations or transactions in the system that access the shared memory or other memories and the caches. For example, one of the processors may initiate a read transaction to read a line of memory. The line of memory may be stored in one or more locations in the system, such as in the shared memory and in one or more of the caches. The memory agents work together to determine the source from which the line of memory should be read for the processor.
The memory agents and memories may be connected in a number of ways, such as by a bus or by a point to point link network using any of a number of suitable protocols. A single memory transaction may therefore be quite complex, involving requests and data being sent back and forth among the multiple memory agents, memories and caches. The sequence of data transmissions depends upon the type of transaction (read, write, etc.), the locations and states of the line of memory in the system, the bus protocol employed, etc. Therefore, testing the operation of the memory agents in the system can be an extremely complex and data-intensive procedure.